1. Technical Field
This disclosure relates to non-volatile memories that employ multiple level cells (MLCs). In particular, this disclosure relates to selective application of different MLC programming techniques to provide a blend of speed and reliability benefits for non-volatile memories.
2. Related Art
Continual development and rapid improvement in semiconductor manufacturing techniques have led to extremely high density memory devices. The memory devices are available in a wide range of types, speeds, and functionality. Memory devices often take the forms, as examples, of flash memory cards and flash memory drives. Today, capacities for memory devices have reached 64 gigabytes or more for portable memory devices such as Universal Serial Bus (USB) flash drives, and one terabyte or more for solid state disk drives. Memory devices form a critical part of the data storage subsystem for digital cameras, digital media players, home computers, and an entire range of other host devices.
In recent years, multiple level cells (MLCs) have been developed and deployed to increase storage capacity. MLCs store charge configurations that define multiple bits of information. For example, a MLC that stores two bits of information is programmable between four different charge configurations. Such an MLC typically is conceptually divided into a lower page that stores, for example, the least significant bit of the two bits stored in the MLC, and an upper page that stores, for example, the most significant bit. In some instances, the lower pages are written first, and when the upper pages in specific MLCs are needed to store additional data, a programming technique adjusts the charge configuration in the specific MLCs to represent multiple bits.
In the past, the programming technique that adjusted the charge configuration rendered the data in the lower page susceptible to corruption or ambiguity when, for example, a write abort occurred. Prior attempts to address this problem included reading the lower page data and saving it in a separate location. Then, if the upper page write was aborted, the lower page data could be recovered. This had both a performance and endurance penalty. Another attempt avoided writing the upper page data if the lower page data already had data, and this approach also incurred a performance and endurance penalty. Yet another attempt included using a battery to ensure that the memory device had enough power to complete a write. However, including a battery was expensive and impractical for small form factor devices. Recently, a “B-state first” programming technique has been developed, as described, for example, in U.S. Pat. Pub. No. 2010-0246260 A1. The B-state first technique has a performance penalty, however, due to the two-pass charge configuration programming technique executed when programming the second bit stored in the MLC.